This invention relates to memory devices, and, more particularly, to memory devices employing an open-array architecture.
Memory devices, such as dynamic random access memories (xe2x80x9cDRAMsxe2x80x9d), include one or more arrays of memory cells arranged in rows and columns. Each array may be divided into several sub-arrays. Typically, one or more digit or xe2x80x9cbitxe2x80x9d lines are provided for each column of the array, and each digit line is coupled to a respective sense amplifier. Each sense amplifier is generally a differential amplifier that compares the voltage at one of its inputs to the voltage at the other of its inputs. The sense amplifier then drives its inputs to complementary logic levels corresponding to the sensed differential voltage.
There are currently two array architectures that are commonly used in memory devices, such as DRAMs. In an xe2x80x9copen-arrayxe2x80x9d architecture, the digit lines span two adjacent subarrays, and each digit line is coupled to each memory cell in a respective column. A sense amplifier is coupled to the digit lines of two adjacent subarrays. Thus, each sense amplifier is shared by two subarrays so that one input to the sense amplifier is coupled to the digit line of one array and the other input to the sense amplifier is coupled to the digit line of the other array. Prior to a memory read operation, the digit lines are precharged to a voltage that is typically one-half the supply voltage, a voltage known as DVC2.
In response to a memory read operation, one of the digit lines coupled to a sense amplifier is coupled to a memory cell being read. In response, the voltage on the digit line either increases or decreases from DVC2 depending upon the logic level stored in the memory cell. The other digit line remains at the precharge voltage, DVC2. The sense amplifier detects that the voltage on the digit line coupled to the memory cell being read has either increased or decreased relative to the precharge voltage and then drives the digit lines to complimentary logic levels corresponding to the sensed voltage.
The other architecture that is commonly used in memory device arrays is the folded digit line architecture. In a folded digit line architecture, each column is provided with a pair of complimentary digit lines, and the digit lines of each pair are generally coupled to alternate memory cells in the same subarray. The complimentary digit lines are coupled to the inputs of a respective sense amplifier. Thus, the digit lines coupled to each sense amplifier are from the same subarray.
A memory read operation in a folded digit line architecture is essentially the same as in an open-array architecture. More specifically, the digit lines of each column are initially precharged to DVC2. In response to a memory read command, one of the digit lines coupled to the sense amplifier is coupled to a memory cell being read. In response, the voltage on the digit line either increases or decreases depending upon the logic level stored in the memory cell. The other digit line remains at the precharge voltage. The sense amplifier detects that the voltage on the digit line coupled to the memory cell being read has either increased or decreased relative to the precharge voltage. The sense amplifier then drives both digit lines to complementary logic levels corresponding to the sensed voltage.
Each of the above-described architectures has its advantages and disadvantages. A disadvantage of the open-array architecture relative to the folded digit line architecture is that it is susceptible to errors resulting from noise because each sense amplifier input is coupled to a different array. In contrast, since both digit lines coupled to a sense amplifier in a folded digit line architecture extend closely adjacent each other through the same array, they tend to pick up the same noise signals. The differential operation of the sense amplifiers thus makes them insensitive to these common mode noise signals.
Although folded digit line architectures have better noise immunity, they have a significant disadvantage compared to open-array architectures in that they are less efficient. Due to the nature of the layout of a folded architecture, each memory cell occupies 8F2 in area, where xe2x80x9cFxe2x80x9d is the minimum feature size of the semiconductor process. The layout of an open array architecture allows for a 6F2 cell area, thereby resulting in a 25% reduction over the 6F2 cell. Thus, open-array architectures are theoretically substantially more efficient than folded digit line architectures in using the surface area of a semiconductor die.
In practice, the theoretical efficiency of an open-array architecture is not achieved because the digit lines, and memory cells to which they are coupled, remain unused for reasons that will be explained with reference to FIG. 1. As shown in FIG. 1, a memory array 10 having a typical open-array architecture includes a plurality of sub arrays 12, 14, 15 . . . N. Positioned between each subarray is a set of sense amplifiers 30, 32, 34 . . . M, one of which is provided for each column of the subarrays. Each of the sense amplifiers 30-M has a differential input. As explained previously, each sense amplifier 30-M is coupled to a digit line D of one sub array and to a digit line D of an adjacent subarray. Thus, each sense amplifier 30-M is shared by adjacent subarrays 12-N. (It will be understood that FIG. 1 shows only a portion of the array 10, which could include a greater or lesser number of subarrays and columns than shown therein.)
As mentioned previously, in an open-array architecture, each sense amplifier is shared by digit lines in adjacent arrays. However, there is no adjacent array for alternate digit lines in the end array N. As a result, there are no adjacent array digit lines that could be coupled to a sense amplifier coupled to alternate digit lines in the end array N. As a result, these xe2x80x9corphanedxe2x80x9d digit lines 50, as well as the memory cells (not shown) coupled to these digit lines 50, remain unused. The inability to use orphaned digit lines in the end subarrays of an open-array architecture reduces the actual efficiency of such architectures from the theoretical efficiency that might otherwise be achieved.
There is therefore a need for a more efficient open-array architecture so that close to the theoretical efficiency of an open-array architectures may be achieved.
A memory array includes a plurality of memory cells, sense amplifiers and digit lines. The memory array has an open-array architecture in which each digit line in the array, except for a set of digit lines at an end of the array, is coupled to a first input of a respective sense amplifier, and a second input of each sense amplifier is coupled to an adjacent digit line. A set of digit lines at the end of the array is coupled to one input of a second plurality of respective sense amplifiers. A second input of each of the sense amplifiers in the second plurality is coupled to a respective load circuit. Each load circuit has an impedance that may be adjusted so that the capacitance at the second input of each sense amplifier is substantially equal to the capacitance at the first input of the sense amplifier. The array may be divided into a plurality of sub-arrays, with the digit lines at the end of the array being in an end sub-array. The array is preferably used in a dynamic random access memory device, and such memory device may be used in a computer system.